Chip timing synchronization in an all-digital band-limited DS/SS modem

A noncoherent digital delay lock loop (D-DLL) suited for code tracking in direct-sequence/spread-spectrum (DS/SS) band-limited (BL) signals is presented and analyzed. The key feature of this tracking scheme is the requirement of only one example per chip to derive the loop error signal. The expression of the S-curve of the proposed scheme is derived theoretically and checked by a time-domain computer simulation. Moreover, the steady-state RMS chip timing jitter of the D-DLL is derived, and results are compared with computer simulations. The proposed synchronization scheme is shown to bear smaller chip timing jitter when compared to the analog scheme for rectangular shaped chips