Title :
Application of a redefinable symbolic simulation technique in VLSI testability design rules checking
Author :
Hirech, M. ; Florent, O. ; Greiner, A. ; Rejouan, E.
Author_Institution :
Lab. MASI, Univ. Pierre et Marie Curie, Paris, France
Abstract :
Symbolic simulation approach is well suited for VLSI design for testability rules checking. Unfortunately the existing techniques are not extensible and therefore the verification tools based on them can not face up to the evolution of rules. This paper discusses the need of this kind of method and then describes a new symbolic simulation in which symbolic information is separated from the simulation algorithm and considered as redefinable data to cope with the extension of rules and different design methodologies
Keywords :
VLSI; application specific integrated circuits; circuit analysis computing; design for testability; formal verification; symbol manipulation; Design For Testability; VLSI testability design rules checking; redefinable data; redefinable symbolic simulation technique; verification tools; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Design automation; Design for testability; Design methodology; Registers; Signal design; Very large scale integration;
Conference_Titel :
Simulation Symposium, 1994., 27th Annual
Conference_Location :
La Jolla, CA
Print_ISBN :
0-8186-5620-4
DOI :
10.1109/SIMSYM.1994.283090
