DocumentCode
1721995
Title
Delay-time bounds and waveform bounds for RLCG ladder networks
Author
Bai, Ymg-Wen ; Zukowski, Charles A.
Author_Institution
Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
fYear
1994
Firstpage
23
Lastpage
30
Abstract
We propose a current-voltage relaxation method to obtain and refine the waveform bounds for RLCG ladder networks. In addition to the known upper bounds, we find the lower bounds, and combine the two to find delay-time bounds for RLCG ladder networks
Keywords
delays; ladder networks; RLCG ladder networks; VLSI interconnections; chip clock rates; current-voltage relaxation method; delay-time bounds; waveform bounds; Delay effects; Delay estimation; Inductors; Integrated circuit interconnections; Integrated circuit modeling; Laplace equations; Propagation delay; Relaxation methods; Upper bound; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation Symposium, 1994., 27th Annual
Conference_Location
La Jolla, CA
Print_ISBN
0-8186-5620-4
Type
conf
DOI
10.1109/SIMSYM.1994.283116
Filename
283116
Link To Document