Abstract :
The following topics are dealt with: process variations aware design; physical design; ATPG and fault tolerance; SOC and NOC design; digital design methods; ASIC and FPGA design; design verifications; analog test; BIST and MEMS test; and SOC and memory tests.
Keywords :
automatic test pattern generation; built-in self test; circuit CAD; fault tolerant computing; field programmable gate arrays; formal verification; integrated circuit design; integrated circuit testing; logic design; logic testing; micromechanical devices; network-on-chip; system-on-chip; ASIC; ATPG; BIST; FPGA design; MEMS test; NOC design; SOC design; SOC test; analog test; design verifications; digital design methods; fault tolerance; memory test; physical design; process variations aware design;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Conference_Location :
Bratislava
Print_ISBN :
978-1-4244-2276-0
DOI :
10.1109/DDECS.2008.4538736
