Implementation of DPL-DD Model for the Simulation of Nanoscale MOS Devices

This paper investigates electrothermal aspects of high-k material as well as silicon-on-insulator (SoI) technology in the nanoscale nMOSFET by the numerical simulation of dual-phase-lag (DPL) heat conduction model under the effect of self-heating phenomenon. Three types of MOS devices including bulk, SoI, and high-k MOSFETs are considered. All of the electrothermal parameters are considered temperature-dependent, and three solution schemes including drift-diffusion (DD), hydrodynamic models, and the Monte Carlo method are compared. Consequently, the DPL-DD model is detected suitable to model the device with 100-nm gate length and Kn=3. The reason lies in low computational cost and high ability of the DPL-DD model to combine the advantages of the DPL-based thermal equation with the semiconductor equations to model the nanoscale phonon transport in the transistor. The temperature-jump boundary condition is applied on all boundaries to consider the boundary phonon scattering phenomenon. The output characteristics along with the temperature field are presented, and the effect of using high-k material on the electrothermal behavior of the transistor has been investigated. It is found that by changing the high-k gate dielectric material, the hotspot temperature decreases, and consequently, the thermal performance of the device increases.