• DocumentCode
    1723944
  • Title

    A radix-2/3/22/23 MDC architecture for variable-length FFT processors

  • Author

    Hsin-Fu Luo ; Ming-Der Shieh ; Kun-Hsien Lee

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • fYear
    2015
  • Firstpage
    180
  • Lastpage
    181
  • Abstract
    A radix-2/3/22/23 multi-path delay commutator (MDC) architecture for pipelined shared-memory fast Fourier transform (FFT) processors is proposed. By using an effective memory addressing scheme, the original processing and control characteristics of the 2m-point FFT processor are retained when processing 3·2m-point FFT, where m is an integer. The proposed variable-length FFT processor can thus be implemented more efficiently.
  • Keywords
    fast Fourier transforms; memory architecture; pipeline arithmetic; shared memory systems; 2m-point FFT processor; 3·2m-point FFT processing; effective memory addressing scheme; multipath delay commutator architecture; pipelined shared-memory fast Fourier transform processors; radix-2/3/22/23 MDC architecture; variable-length FFT processors; Delays; Hardware; Memory management; Process control; Program processors; Radiation detectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Consumer Electronics - Taiwan (ICCE-TW), 2015 IEEE International Conference on
  • Conference_Location
    Taipei
  • Type

    conf

  • DOI
    10.1109/ICCE-TW.2015.7216843
  • Filename
    7216843
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1723944