Author :
Liu, Q. ; Yagishita, A. ; Loubet, N. ; Khakifirooz, A. ; Kulkarni, P. ; Yamamoto, T. ; Cheng, K. ; Fujiwara, M. ; Cai, J. ; Dorman, D. ; Mehta, S. ; Khare, P. ; Yako, K. ; Zhu, Y. ; Mignot, S. ; Kanakasabapathy, S. ; Monfray, S. ; Boeuf, F. ; Koburger, C.
Abstract :
We present UTBB devices with a gate length (LG) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (Vbb) enables Vt modulation of more than 125mV with a Vbb of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-Vt and power management applications. We explore the impact of GP, BOX thickness and Vbb on local Vt variability for the first time. Excellent AVt of 1.27 mV·μm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (Ig) and lower external resistance (Rext), thanks to a thicker inversion gate dielectric (Tinv) and body (Tsi) thickness.
Keywords :
CMOS integrated circuits; leakage currents; BOX fully depleted device integration; BOX thickness; UTBB devices; back bias; external resistance; gate leakage; gate-first high-k/metal; inversion gate dielectric; power management; raised source/drains; size 22 nm; size 25 nm; ultra-thin-body; Doping; International Electron Devices Meeting; Logic gates; Modulation; Performance evaluation; Resource description framework; Simulation;
