• DocumentCode
    17260
  • Title

    Methodology for Cycle-Accurate DRAM Performance Analysis

  • Author

    Ikodinovic, Igor

  • Author_Institution
    Dept. of Multimedia Archit. & Performance, Qualcomm, Markham, ON, Canada
  • Volume
    64
  • Issue
    7
  • fYear
    2015
  • fDate
    July 1 2015
  • Firstpage
    2084
  • Lastpage
    2091
  • Abstract
    A new methodology for DRAM performance analysis has been proposed based on accurate characterization of DRAM bus cycles. The proposed methodology allows cycle-accurate performance analysis of arbitrary DRAM traces, obviates the need for functional simulations, allows accurate estimation of DRAM performance maximum, and enables root causing of suboptimal DRAM operation.
  • Keywords
    DRAM chips; DRAM bus cycles; arbitrary DRAM traces; cycle-accurate DRAM performance analysis; functional simulation; suboptimal DRAM operation; Analytical models; Computational modeling; Performance analysis; Performance evaluation; Protocols; Random access memory; Timing; DRAM; formal models; modeling methodologies; performance analysis and design aids;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2014.2346184
  • Filename
    6873278