DocumentCode :
1726631
Title :
A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory
Author :
Choi, Sung-Jin ; Han, Jin-Woo ; Kim, Sungho ; Moon, Dong-Il ; Jang, Moongyu ; Choi, Yang-Kyu
Author_Institution :
EECS, KAIST, Daejeon, South Korea
fYear :
2010
Firstpage :
111
Lastpage :
112
Abstract :
A dopant segregated Schottky barrier (DSSB) TFT SONOS device is demonstrated for the application of 3D TFT logic devices and flash memory. To apply the DSSB to 3D TFT flash memory, a novel spacer-free structure is successfully implemented. The DSSB TFT SONOS shows a good distribution of programmed VT by one-time programming with high-speed (a VT shift of 2.9 V @ 32 ns) due to the use of a unique local injection of carriers from the DSSB S/D junctions and it is not affected by grain boundaries. Moreover, the program speed is accelerated by reduction of the fin width owing to the enhanced field.
Keywords :
Schottky barriers; energy gap; flash memories; logic circuits; thin film transistors; 3D TFT flash memory; 3D TFT logic devices; DSSB S/D junctions; dopant segregated Schottky barrier TFT SONOS device; grain boundary; lateral engineered bandgap; one-time programming; spacer-free structure; Decision support systems; Junctions; Logic gates; Programming; SONOS devices; Thin film transistors; Three dimensional displays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
Type :
conf
DOI :
10.1109/VLSIT.2010.5556191
Filename :
5556191
Link To Document :
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