• DocumentCode
    1727271
  • Title

    Electromigration reliability of redistribution lines in wafer-level chip-scale packages

  • Author

    Lai, Yi-Shao ; Kao, Chin-Li ; Chiu, Ying-Ta ; Appelt, Bernd K.

  • Author_Institution
    ASE Group, Kaohsiung, Taiwan
  • fYear
    2011
  • Firstpage
    326
  • Lastpage
    331
  • Abstract
    Wafer-level chip-scale packages (WLCSPs) have become subject to the same drive for miniaturization as all electronic packages. The I/O count is increasing and ball pitch is shrinking at the expense of trace pitch and in turn, current densities are increasing. This leads to current crowding and Joule heating in the vicinity of solder joints and under bump metallurgy (UBM) structures where resistance values change significantly. These phenomena are responsible for structural damage of redistribution line (RDL)/UBM and UBM/solder interconnects due to ionic diffusion or electromigration. In this work, sputtered Al and electroplated Cu RDLs are examined and quantified by three-dimensional electrothermal coupling analysis. Results provide a guideline for estimating maximum allowable currents and electromigration lifetime.
  • Keywords
    chip scale packaging; electromigration; metallurgy; wafer level packaging; electromigration reliability; electronic packages; electrothermal coupling analysis; ionic diffusion; redistribution lines; solder joints; under bump metallurgy; wafer-level chip-scale packages; Copper; Current density; Electromigration; Mathematical model; Soldering; Temperature measurement; Vehicles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
  • Conference_Location
    Lake Buena Vista, FL
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-61284-497-8
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2011.5898533
  • Filename
    5898533