Title :
A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers
Author :
Liao, M.-J. ; Su, C.-F. ; Chang, C.-Y. ; Wu, Allen C -H
Author_Institution :
Dept. Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
fDate :
6/24/1905 12:00:00 AM
Abstract :
We present a carry-select-adder partitioning algorithm for high-performance Booth-encoded Wallace-tree multipliers. By taking into account various data arrival times, we propose a branch-and-bound algorithm and a heuristic to partition an n-bit carry-select adder into a number of adder blocks such that the overall delay of the design is minimized. The experimental results show that our proposed algorithm can achieve on average 9.12% delay reduction with less than 1% of area overhead on 15 multipliers ranges from 16×6-bit to 64×64-bit.
Keywords :
adders; carry logic; delays; logic partitioning; multiplying circuits; tree searching; 16 bit; 64 bit; Booth-encoded Wallace-tree multipliers; area overhead; branch-and-bound algorithm; carry-select-adder optimization technique; overall delay; partitioning algorithm; Adders; Algorithm design and analysis; Circuits; Computer science; Delay effects; Heuristic algorithms; Multiplexing; Partitioning algorithms; Signal processing algorithms; Timing;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1009782
