Design of oversampling current steering DAC with 640 MHz equivalent clock frequency

Author

Choi, Yunyoung ; Maloberti, Franco

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

Volume

1

fYear

2002

fDate

6/24/1905 12:00:00 AM

Abstract

Recent mobile communications demand high-speed and high-resolution data converters for digital signal processing (DSP) in the receiver and transceiver of the communication systems. Those applications require more than 14-bit resolution and several hundred of MHz bandwidth. In this paper, we propose a new sigma-delta parallel DAC (Digital-to-Analog Converter) structure that achieves the required accuracy with 640 MHz clock frequency. The circuit employs current steering and multi-bit solution with matching technique. The entire architecture has been verified by simulations with a 0.18 μm CMOS process (TI).

Keywords

CMOS integrated circuits; digital-analogue conversion; high-speed integrated circuits; mobile communication; sigma-delta modulation; 0.18 micron; 14 bit; 640 MHz; CMOS process; DSP; digital signal processing; digital-to-analog converter structure; high-resolution data converters; high-speed data converters; mobile communications; multi-bit DAC; oversampling current steering DAC; sigma-delta parallel DAC; Bandwidth; Circuits; Clocks; Delta-sigma modulation; Digital signal processing; Digital-analog conversion; Frequency conversion; Mobile communication; Signal resolution; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1009789

Filename

1009789