Title :
Metal inserted poly-Si with high temperature annealing for achieving EOT of 0.62nm in La-silicate MOSFET
Author :
Kawanago, T. ; Lee, Y. ; Kakushima, K. ; Ahmet, P. ; Tsutsui, K. ; Nishiyama, A. ; Sugii, N. ; Natori, K. ; Hattori, T. ; Iwai, H.
Author_Institution :
Frontier Res. Center, Tokyo Inst. of Technol., Yokohama, Japan
Abstract :
This paper reports device process approach for further EOT scaling with small interface state density based on controlling La-silicate/Si interface. The interface state density of 1.6 × 1011 cm-2 eV-1 can be achieved by annealing at 800°C for 30 min in forming gas while significant increase in EOT has been also observed. EOT increase caused by high temperature annealing has been drastically inhibited with MIPS stacks accompanied by high quality interface. The effective electron mobility of 155 cm2/Vsec at 1 MV/cm with an EOT of 0.62 nm has been obtained in direct contact La-silicate/Si structure by combination of MIPS stacks with high temperature annealing.
Keywords :
MOSFET; annealing; electron mobility; elemental semiconductors; high-temperature electronics; lanthanum compounds; silicon; EOT scaling; La2O3-Si; MIPS stacks; MOSFET; Si; effective electron mobility; equivalent oxide thickness; high temperature annealing; metal inserted poly-Si stacks; size 0.62 nm; small interface state density; temperature 800 degC; time 30 min; Annealing; Electron mobility; Interface states; Logic gates; MOSFET circuits; Silicon; Tin;
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European
Conference_Location :
Helsinki
Print_ISBN :
978-1-4577-0707-0
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2011.6044233
