LED packaging using silicon substrate with cavities for phosphor printing and copper-filled TSVs for 3D interconnection

A novel wafer level packaging process for phosphor converted LED is presented in this paper. The core of this process is the fabrication of a silicon substrate with cavities for phosphor printing and through-silicon copper pillars for 3D interconnection. A double-side polished 4-inch wafer is used as the substrate. In the present process, DRIE is applied to the back side of the silicon wafer firstly for forming blind vias. The next step is to perform DRIE from the front side to create cavities for LED chip mounting and phosphor printing. Copper is then electroplated to fill the blind vias to form copper pillars. After the copper plating, KOH etching is applied to the front side to further etch the cavities in order to expose the embedded copper pillars. Afterwards, solder is plated on the exposed tips of copper pillars at the bottom of the cavities. Finally, the copper overburden on the back side of the wafer is patterned as the redistribution layer for the next level of interconnection. Subsequent to the fabrication of silicon substrate, blue LEDs are flip-chip mounted on the pre-plated solder bumps in the cavities. Reflow soldering is then conducted to fix the LED chips. Following an epoxy dispensing process, yellow phosphor powder is printed into the cavity for color tuning. The pre-dispensed epoxy is then UV-cured to serve as the phosphor powder binder and the LED chip encapsulant. The present configuration offers a structure with low profile and compact footprint for LED wafer level packaging. The fabrication process is described in detail in this paper.