Air cavity low-loss transmission lines for high speed serial link applications

This paper reports on the design, optimization, processing and measurement of an air-cavity transmission line structure on FR-4 boards for high-speed chip-to-chip links. The proposed structure has air as the insulating material, thereby minimizing the dielectric loss. Full-wave electromagnetic simulation is used to predict the performance of the proposed air-cavity structure. Compared to conventional transmission lines on an FR4 substrate, the effective dielectric constant is reduced by 25% from 2.75 to 2.07, and the dielectric loss is reduced by 26% from 0.48 dB/cm (1.22 dB/inch) to 0.35 dB/cm (0.9 dB/inch) at 20 GHz. Simulation also shows that conductor surface roughness contributes significant loss, which is confirmed by the measurement results. An active low power electrical link demonstration is also reported herein. The transmitter (TX) utilizes a 1-tap feed-forward-equalization (FFE) for pre-cursor cancellation and the receiver (RX) a 1-tap decision-feedback-equalization (DFE) for post-cursor cancellation. The TX and RX frontends implement a current-sharing scheme to reduce the overall link power consumption. The circuitry and interconnect were co-designed to achieve 6.25 Gb/s at ~0.6 mW/Gb/s (or 0.6 pJ/bits) in 0.13 μm 1.2V CMOS process.