The challenges and progress of USJ formation & process integration for 32nm technology and beyond

Author

Tseng, Hsing-Huang ; Kalra, Pankaj ; Oh, Jungwoo ; Majhi, Prashant ; Liu, Tsu-Jae King ; Jammy, Raj

Author_Institution

Semicond. Manuf. Technol. (SEMATECH), Austin, TX

fYear

2008

Firstpage

3

Lastpage

6

Abstract

Future devices will be fabricated with high-k/metal gate stack and possibly employ high mobility channel materials. Ultra shallow junction (US J) research targeted for devices scaled to 32 nm and beyond should address the compatibility with the advanced gate stack and new channel materials. This paper discusses recent progress in USJ formation targeted for future Si and Ge channel devices. Challenges of USJ module for scaled CMOS technologies will be highlighted.

Keywords

CMOS integrated circuits; elemental semiconductors; germanium; nanotechnology; silicon; high mobility channel materials; high-k/metal gate stack; nanofabrication; nanotechnology; process integration; scaled CMOS technology; size 32 nm; ultra shallow junction; Annealing; CMOS technology; Contact resistance; Gate leakage; High K dielectric materials; High-K gate dielectrics; III-V semiconductor materials; MOSFETs; Silicon; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology, 2008. IWJT '08. Extended Abstracts - 2008 8th International workshop on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-1737-7

Electronic_ISBN

978-1-4244-1738-4

Type

conf

DOI

10.1109/IWJT.2008.4540005

Filename

4540005