Closed-form expressions for modeling metal fill effects in interconnects

This paper demonstrates efficient methods to account for parasitic capacitance and eddy-current loss in on-chip interconnects due to square metal fill. The parasitic capacitance extraction is based on an effective 3D to 2D reduction approach while the eddy-current loss in in-plane and out-of-plane metal fill is estimated by an empirical formula developed over a wide range of dimensions and frequencies. The interconnect capacitance matches with 3D electrostatic simulation and measurement within 2.1%. The additional parasitic resistance due to eddy-current loss in metal fill matches within 10% with 3D quasi-magnetostatic simulation results.