Signal margin test to identify process sensitivities relevant to DRAM reliability and functionality at low temperatures

Author

Nelson, E. ; Li, Y. ; Poindexter, D. ; Ruprecht, M. ; Lim, E. ; Matsubara, Y. ; Sawazaki, H. ; Ye, Qiaoyang ; Iwatake, M. ; Tonti, W.

Author_Institution

IBM Microelectron., Essex Junction, VT, USA

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

6

Lastpage

9

Abstract

With high aspect ratio, tight spacing, small line widths, and low supply voltages associated with the scaling of the DRAM cell, signal for the sense amplifier becomes weaker for each new DRAM generation. We have developed a signal margin testing methodology capable of identifying process sensitivities relevant to DRAM functionality and reliability at low temperatures. This paper describes the test methodology and discusses the benefits derived from applying this method to 256M DRAM product development

Keywords

DRAM chips; integrated circuit reliability; integrated circuit testing; 256 MB; DRAM cell; DRAM reliability; functionality; high aspect ratio; low supply voltages; low temperatures; process sensitivities; scaling; sense amplifier; signal margin test; signal margin testing methodology; small line widths; test methodology; tight spacing; Capacitance; FETs; Low voltage; Physics; Random access memory; Rivers; Signal processing; Temperature distribution; Temperature sensors; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 1999. IEEE International

Conference_Location

Lake Tahoe, CA

Print_ISBN

0-7803-5649-7

Type

conf

DOI

10.1109/IRWS.1999.830551

Filename

830551