Abstract :
A hundredfold increase of scan data volume has been predicted for the next ten years. This position statement discusses the implications on ATE and EDA, within the constraints of test cost, quality, and time-to-market. The first conclusion will be that the demand for more scan data can be met without increasing test cost, by exploiting test data sharing across multiple equal cores, relying on improved test data compression, and on faster scan I/O, served by deeper ATE memory. But will this provide sufficient test coverage? It seems too challenging to create effective, up-to-date fault models and suitable scan test conditions such that practical ATPG alone can successfully target all defects in future complex heterogeneous SiP and 3D packages. Additional new test methodologies will be needed to test devices under stressful realistic conditions. ATE must provide well controllable stress test conditions and interact with the DUT at a higher level of abstraction to enable fast development of system-like tests.
Keywords :
automatic test equipment; automatic test pattern generation; ATE; ATPG; EDA; automatic test equipment; realistic tests; scan data volume; system like tests; Automatic test pattern generation; CMOS technology; Costs; Electronic design automation and methodology; Packaging; Pins; Stress control; System testing; Test data compression; Time to market;
