DocumentCode
1738
Title
Parallel AES Encryption Engines for Many-Core Processor Arrays
Author
Bin Liu ; Baas, Bevan M.
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of California, Davis, Davis, CA, USA
Volume
62
Issue
3
fYear
2013
fDate
Mar-13
Firstpage
536
Lastpage
547
Abstract
By exploring different granularities of data-level and task-level parallelism, we map 16 implementations of an Advanced Encryption Standard (AES) cipher with both online and offline key expansion on a fine-grained many-core system. The smallest design utilizes only six cores for offline key expansion and eight cores for online key expansion, while the largest requires 107 and 137 cores, respectively. In comparison with published AES cipher implementations on general purpose processors, our design has 3.5-15.6 times higher throughput per unit of chip area and 8.2-18.1 times higher energy efficiency. Moreover, the design shows 2.0 times higher throughput than the TI DSP C6201, and 3.3 times higher throughput per unit of chip area and 2.9 times higher energy efficiency than the GeForce 8800 GTX.
Keywords
cryptography; multiprocessing systems; AES cipher implementations; advanced encryption standard cipher; data-level; energy efficiency; fine-grained many-core system; general purpose processors; many-core processor arrays; offline key expansion; online key expansion; parallel AES encryption engines; task-level parallelism; Clocks; Computer architecture; Delay; Encryption; Hardware; Software algorithms; Throughput; Advanced encryption standard (AES); AsAP; fine-grained; many-core; parallel processor; software; synchronous dataflow;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2011.251
Filename
6112748
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