Flexible processor based on full-adder/D-flip-flop merged module

Author

Sakaidani, Satoshi ; Miyamoto, Naoto ; Ohmi, Tadahiro

Author_Institution

Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan

fYear

2001

fDate

2001

Firstpage

35

Lastpage

36

Abstract

Flexible processor based on full-adder/D-flip-flop merged module (FDMM) has been designed and fabricated. The developed FDMM has unique ability to perform both logic and flip-flop functions with a small transistor count by merging the common part of both circuits. We have also developed a context memory block to reconfigure the hardware dynamically. The flexible processor may fill a gap between hardware performance and software programmability to jump into novel computing such as software/hardware synthesis; “software accelerator”

Keywords

CMOS digital integrated circuits; VLSI; adders; digital signal processing chips; flip-flops; reconfigurable architectures; 0.6 micron; VLSI chip; context memory block; dynamic reconfiguration; flexible processor; flip-flop functions; full-adder/D-flip-flop merged module; logic functions; software/hardware synthesis; submicron CMOS technology; Acceleration; CMOS technology; Design engineering; Field programmable gate arrays; Flip-flops; Hardware; Large scale integration; Logic circuits; Reconfigurable logic; Software performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913276

Filename

913276