DocumentCode
1743989
Title
Factorization to enhance random pattern testability of EXOR based circuits
Author
Ishhikawa, R. ; Hirayanna, T. ; Koda, Goro ; Shimizu, Kensuke
Author_Institution
Dept. of Comput. Sci., Gunma Univ., Japan
fYear
2000
fDate
2000
Firstpage
795
Lastpage
798
Abstract
This paper describes a testable design for random pattern testing. Factorization is one of the basic techniques in the testable design. Factorization of AND and OR based expressions has been studied for years, and EXOR operations have been used in the logical design. We propose factorizations based on EXOR operations widely used recently. The experimental results show that the average of the decreasing rate of the tests is 18% and our methods are effective in enhancing the random pattern testability
Keywords
design for testability; logic circuits; logic design; logic gates; logic testing; probability; EXOR based circuits; EXOR operations; factorizations; logic design; random pattern testability; testable design; Automatic testing; Circuit faults; Circuit testing; Computer science; Design engineering; Electrical fault detection; Electronic equipment testing; Electronic mail; Fault detection; Logic testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location
Tianjin
Print_ISBN
0-7803-6253-5
Type
conf
DOI
10.1109/APCCAS.2000.913640
Filename
913640
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