Title :
A 10-bit, 20 Ms/s, 22 mW folding and interpolating CMOS ADC
Author :
Nabavi, A.R. ; Dabbagh, K.
Author_Institution :
Dept. of Electr. Eng., Tarbiat Modares Univ., Tehran, Iran
Abstract :
This paper presents a 10 bit, low-power, 3.3 V folding and interpolating analog-to-digital converter (ADC). In this ADC, folder blocks with high folding factor are designed using a low-power, 3.3 V four-level folder to achieve the desired resolution. Also, the interpolation circuit and the current comparator are optimized for high accuracy and low-power consumption. The ADC is implemented in a 1.2 μm CMOS technology, and measures 1.7 mm×1 mm (without pads). The results of HSPICE simulation with the level-39 MOSFET model illustrate a conversion rate of 20 Ms/s for a 2 MHz input signal, and a power dissipation of 22 mW from a single 3.3 V supply
Keywords :
CMOS integrated circuits; MOSFET; SPICE; analogue-digital conversion; circuit optimisation; circuit simulation; current comparators; integrated circuit design; integrated circuit modelling; interpolation; low-power electronics; 1 mm; 1.2 micron; 1.7 mm; 10 bit; 2 MHz; 22 mW; 3.3 V; ADC; CMOS technology; HSPICE simulation; MOSFET model; analog-to-digital converter; conversion rate; current comparator; folder blocks; folding factor; folding/interpolating CMOS ADC; four-level folder; input signal; interpolation circuit; low-power ADC; optimization; power consumption; power dissipation; signal resolution; Analog-digital conversion; CMOS technology; Circuit simulation; Interpolation; MOSFET circuits; Power MOSFET; Power dissipation; Semiconductor device modeling; Signal resolution; Voltage;
Conference_Titel :
Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on
Conference_Location :
Tehran
Print_ISBN :
964-360-057-2
DOI :
10.1109/ICM.2000.916411
