Low power order based DCT processing algorithm

Author

Masupe, S. ; Arslan, T.

Author_Institution

Dept. of Electron. & Electr. Eng., Edinburgh Univ., UK

Volume

2

fYear

2001

fDate

6-9 May 2001

Firstpage

5

Abstract

This paper presents an algorithm and an associated architecture for the low power implementation of the Discrete Cosine Transform. The algorithm reduces power by manipulating bit-correlation between successive cosine coefficients applied to the input of the Multiply-Accumulate section such that the effective switched capacitance is reduced. This reduces the switching activity in the Discrete Cosine Transform processor. The paper describes the algorithm and the proposed architecture. The evaluation procedure is also presented including the results from a number of example images illustrating up-to 29%, power savings

Keywords

computational complexity; computer architecture; digital signal processing chips; discrete cosine transforms; image processing; DCT processing algorithm; Discrete Cosine Transform; bit-correlation; discrete cosine transform processor; multiply-accumulate section; power savings; successive cosine coefficients; switched capacitance; switching activity; Capacitance; Computational complexity; Discrete cosine transforms; Energy consumption; Flowcharts; Hamming distance; Neck; Power dissipation; Read only memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.920992

Filename

920992