A compatible DCT/IDCT architecture using hardwired distributed arithmetic

Author

Kim, Dae Won ; Kwon, Taeh Won ; Seo, Jung Min ; Yu, Jae Kun ; Lee, Silk Kyu ; Suk, Jung Hee ; Choi, Jun Rim

Author_Institution

Sch. of Electr. Eng., Kyungpook Nat. Univ., Taegu, South Korea

Volume

2

fYear

2001

fDate

6-9 May 2001

Firstpage

457

Abstract

In this paper, we evaluate the hardware implementation method of general DCT/IDCT compatible architecture with minimum resource and high speed. We proposed and implemented the hardwired DA (distributed arithmetic) method with radix-2 multibit coding for the minimum resource, and we used symmetric transpose memory for high speed. Generally, IDCT procedure consists of two ID-IDCT procedures and one transpose. This architecture shows some resources of IDCT core are reusable for DCT process. We propose a general scheme for the processing element of which the gate count is 8.6 K for DCT and 9.2 K for IDCT, through Verilog HDL simulation in 0.65 um SOG technology. Also, we verify that the simulation results using Matlab are acceptable for IEEE Std 1180-1990

Keywords

data compression; discrete cosine transforms; distributed arithmetic; hardware description languages; image coding; multimedia communication; IEEE Std 1180-1990; Matlab; SOG technology; Verilog HDL simulation; compatible DCT/IDCT architecture; hardwired distributed arithmetic; image compression; minimum resource; multimedia; processing element; radix-2 multibit coding; symmetric transpose memory; Arithmetic; Discrete cosine transforms; Electronic mail; Hardware design languages; Kilns; Multimedia communication; Pixel; Redundancy; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921106

Filename

921106