High-speed serial communication with error correction using 0.25 μm CMOS technology

Author

Suutari, Teemu ; Isoaho, Jouni ; Tenhumen, H.

Author_Institution

Dept. of Appl. Phys., Turku Univ., Finland

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

618

Abstract

In this paper we propose a novel design for an autonomous high-speed serial off and on-chip communication system which incorporates impedance tuning, error correction with a packet transfer and a parallel asynchronous interface. The constructed transmitter-receiver pair has throughput of 5 Gbit/s. With error correction and packet transfer overhead accounted for this construct has bandwidth of 500 <bytes/s. The circuit has been simulated using HSpice with 0.25 μm TMSC CMOS technology

Keywords

CMOS integrated circuits; SPICE; ULSI; circuit simulation; crosstalk; error correction; high-speed integrated circuits; integrated circuit interconnections; 0.25 micron; 5 Gbit/s; HSpice; IC interconnects; TMSC CMOS technology; ULSI; crosstalk; error correction; high-speed serial communication; impedance tuning; packet transfer overhead; parallel asynchronous interface; transmitter-receiver pair; Bit error rate; CMOS technology; Crosstalk; Delay; Error correction; Error correction codes; Integrated circuit interconnections; Power system interconnection; Throughput; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922313

Filename

922313