Implementation of encryption algorithms on transport triggered architectures

Author

Hamalainen, P. ; Hannikainen, M. ; Hamalainen, Timo ; Corporaal, H. ; Saarvinen, J.

Author_Institution

Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

726

Abstract

The paper studies a configurable processor architecture, transport triggered architecture (TTA), for encryption algorithm implementations. The automatic TTA design space exploration is applied and configurations with good cost-performance ratio are found. It is shown that TTAs are at least equal to commercial processors in performance. According to earlier studies the performance level is also achieved at far lower cost. This encourages further development with tuned functionality

Keywords

cryptography; microprocessor chips; parallel architectures; reconfigurable architectures; configurable processor architecture; cost; cost-performance ratio; design space exploration; encryption algorithms; performance level; transport triggered architectures; tuned functionality; Central Processing Unit; Communication system security; Computer architecture; Cryptography; Embedded system; Hardware; Laboratories; Multiprocessor interconnection networks; Parallel processing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922340

Filename

922340