DocumentCode
1745335
Title
Split-Gate Logic circuits for multi-threshold technologies
Author
Elrabaa, Muhammad E S ; Elmasry, Mohamed I.
Author_Institution
Dept. of Electr. Eng., United Arab Emirates Univ., Al-Ain, United Arab Emirates
Volume
4
fYear
2001
fDate
6-9 May 2001
Firstpage
798
Abstract
A new dual-Vt static CMOS circuits, the Split-Gate dual-Vt (SG-DVT) logic, are devised. Their performance is compared to that of all-low-Vt, all-high-Vt, and other dual-Vt circuits in terms of speed and energy consumption (both static and dynamic). They achieved speeds close to that of the all-low-Vt circuits, lower leakage (both stand-by and active) than other dual-Vt circuits, and lower leakage dependency on logic block input patterns
Keywords
CMOS logic circuits; threshold logic; SG-DVT logic; active leakage; delay; dual-Vt static CMOS circuit; energy consumption; multi-threshold technology; split-gate logic circuit; stand-by leakage; CMOS logic circuits; CMOS technology; Energy consumption; Feedback control; Leakage current; Logic circuits; MOS devices; Split gate flash memory cells; Threshold voltage; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922358
Filename
922358
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