• DocumentCode
    174656
  • Title

    Software pipelining of dataflow programs with dynamic constructs on multi-core processor

  • Author

    Murarka, Yogesh ; Gode, Pankaj ; Pasupuleti, Sirish Kumar ; Kohli, Shruti

  • Author_Institution
    Samsung R&D Inst. India, Bangalore, India
  • fYear
    2014
  • fDate
    19-22 Oct. 2014
  • Firstpage
    340
  • Lastpage
    347
  • Abstract
    Dataflow programming, which has been traditionally used for DSP application development, has evolved to coarsegrain dataflow programming to support programmable multicore architecture of modern DSPs. Software pipelining is an important scheduling technique to map a coarse-grain dataflow on a multicore architecture. A software pipeline schedule is executed in the self-timed manner on programmable cores. However in presence of conditional paths in a dataflow program, a selftimed execution of a software pipeline schedule can introduce unpredictability in the execution time and degrade the application performance. This paper addresses the problem of computing a software pipeline schedule of dataflow programs with dynamic constructs for self-timed execution on multi-core platforms. In this paper, we present a software pipeline scheduling technique that reduces the variation in execution time across software pipeline iterations. The schedule, when executed in a self-timed manner improves application performance. We present an integer linear programing (ILP) formulation that optimizes the software pipeline schedule. Our ILP formulation models the effect of conditional paths in a dataflow on the execution time of the schedule. Experimental evaluation shows that our solution could reduce the decoding time of a MPEG4 frame by upto 30%.
  • Keywords
    data flow computing; multiprocessing systems; pipeline processing; scheduling; DSP application development; ILP formulation models; MPEG4 frame; coarse-grain dataflow programming; dynamic constructs; execution time; integer linear programing; modern DSP; multicore platforms; multicore processor; programmable cores; programmable multicore architecture; self-timed execution; software pipeline iterations; software pipeline schedule; software pipeline scheduling; software pipelining; Kernel; Multicore processing; Pipeline processing; Pipelines; Processor scheduling; Schedules;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design (ICCD), 2014 32nd IEEE International Conference on
  • Conference_Location
    Seoul
  • Type

    conf

  • DOI
    10.1109/ICCD.2014.6974703
  • Filename
    6974703