A deterministic scan-BIST architecture with application to field testing of high-availability systems

Author

Swaminathan, Shivakumar ; Chakrabarty, Krishnendu

Author_Institution

IBM Microelectron., Research Triangle Park, NC, USA

fYear

2001

fDate

2001

Firstpage

259

Lastpage

262

Abstract

We propose an autonomous, deterministic scan-BIST architecture that allows compact, precomputed test sets with complete fault coverage to be used for field testing. The use of such short test sequences is desirable in safety-critical systems since it reduces the error latency. It also reduces testing time and therefore allows periodic field testing to be carried out with low system downtime. We synthesize the BIST logic for several ISCAS 89 benchmarks and industrial circuit modules and show that the BIST overhead is low in all cases. The proposed design can also be efficiently used with a mixed-mode BIST strategy

Keywords

VLSI; automatic test pattern generation; built-in self test; integrated circuit reliability; integrated circuit testing; logic testing; ATPG; BIST logic; autonomous BIST architecture; compact precomputed test sets; complete fault coverage; deterministic scan-BIST architecture; error latency reduction; field testing; high-availability systems; low BIST overhead; mixed-mode BIST strategy; safety-critical systems; testing time reduction; Application software; Automatic testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Delay; Logic circuits; Logic testing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 2001, IEEE Conference on.

Conference_Location

San Diego, CA

Print_ISBN

0-7803-6591-7

Type

conf

DOI

10.1109/CICC.2001.929768

Filename

929768