A genetic algorithm for testable data path synthesis

Author

Harmanani, H. ; Saliba, R. ; Khoury, M.

Author_Institution

Dept. of Comput. Sci., Lebanese Univ., Beirut, Lebanon

Volume

1

fYear

2001

fDate

2001

Firstpage

235

Abstract

A high level synthesis for testability method is presented with the objective to generate testable resistor transistor logic designs from behavioral descriptions. The approach is formulated as an allocation problem and solved using an efficient genetic algorithm that generates cost-effective testable designs. We follow the allocation method with an automatic test point selection algorithm that trades off design area and delay with test quality. The method is implemented and design comparisons are reported

Keywords

C language; VLSI; automatic testing; combinational circuits; data flow graphs; design for testability; genetic algorithms; high level synthesis; integrated circuit design; integrated circuit testing; integrated logic circuits; logic design; logic testing; allocation problem; automatic test point selection algorithm; behavioral descriptions; cost-effective testable designs; delay; design area; design comparisons; genetic algorithm; high level synthesis for testability method; resistor transistor logic designs; test quality; testable RTL designs; testable data path synthesis; Algorithm design and analysis; Automatic testing; Biological cells; Built-in self-test; Circuit testing; Computer science; Delay; Genetic algorithms; High level synthesis; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2001. Canadian Conference on

Conference_Location

Toronto, Ont.

ISSN

0840-7789

Print_ISBN

0-7803-6715-4

Type

conf

DOI

10.1109/CCECE.2001.933689

Filename

933689