A sub-1V dual-threshold domino circuit using product-of-sum logic

Author

Fujii, Koji ; Douseki, Takakuni ; Kado, Yuichi

Author_Institution

NTT Telecommun. Energy Labs., Kanagawa, Japan

fYear

2001

fDate

2001

Firstpage

259

Lastpage

262

Abstract

A sub-1 V dual-threshold domino circuit is proposed to accelerate the operation of CMOS digital circuits at below 1 V. The circuit combines a low and high threshold-voltage (Vt) MOSFET with standby control to make it possible to achieve high-speed evaluation and low standby leakage current. A low-Vt foot nMOSFET is used to shorten precharge time and increase throughput. A product-of-sum logic form is used for implementation of a pull-down logic to increase the noise margin. An experimental 64-bit carry look-ahead (CLA) adder demonstrated a 0.6 V operation with a standby power of 0.4 μW and a delay time of 4.8 ns

Keywords

CMOS logic circuits; adders; large scale integration; low-power electronics; threshold logic; 0.4 muW; 0.6 to 1 V; 4.8 ns; CLA adder; CMOS LSIs; carrylook-ahead adder; dual-Vt domino circuit; dual-threshold domino circuit; high threshold-voltage MOSFET; high-speed evaluation; low standby leakage current; low threshold-voltage MOSFET; noise margin; product-of-sum logic form; pull-down logic; standby control; Acceleration; Adders; CMOS digital integrated circuits; CMOS logic circuits; Digital circuits; Foot; Leakage current; Logic circuits; MOSFET circuits; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, International Symposium on, 2001.

Conference_Location

Huntington Beach, CA

Print_ISBN

1-58113-371-5

Type

conf

DOI

10.1109/LPE.2001.945412

Filename

945412