DocumentCode :
175154
Title :
A 46.4–58.1 GHz frequency synthesizer featuring a 2nd harmonic extraction technique that preserves VCO performance
Author :
Sadhu, B. ; Ferriss, Mark ; Valdes-Garcia, A.
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
2014
fDate :
1-3 June 2014
Firstpage :
173
Lastpage :
176
Abstract :
This paper introduces a 2nd harmonic extraction technique in a 46.4-58.1 GHz frequency synthesizer. The frequency doubling approach is based on tapping second harmonic signals at the VCO supply and tail nodes and amplifying them to provide a differential output. Since the amplifiers do not load the VCO outputs, neither the tuning range nor the frequency of the VCO is affected. Moreover, a novel noise bypass technique is utilized to ensure that the amplifiers do not degrade the VCO phase noise. As a result, the frequency synthesizer achieves 22.4% tuning range (46.4-58.1 GHz) and phase noise below -118dBc/Hz while consuming 66mW power from a 1V supply. The synthesizer occupies 0.6mm×1mm in IBM 32SOI CMOS.
Keywords :
CMOS analogue integrated circuits; differential amplifiers; frequency synthesizers; integrated circuit noise; millimetre wave integrated circuits; millimetre wave oscillators; phase noise; voltage-controlled oscillators; 2nd harmonic extraction technique; IBM 32SOI CMOS; VCO; amplifier; differential output; frequency 46.4 GHz to 58.1 GHz; frequency doubling approach; frequency synthesizer; noise bypass technique; phase noise; power 66 mW; second harmonic signal tapping; voltage 1 V; Harmonic analysis; Phase noise; Power amplifiers; Power generation; Tuning; Voltage-controlled oscillators; 60GHz; PLL; VCO; doubler; frequency multiplier; mm-wave; phase noise; synthesizer; tuning range;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radio Frequency Integrated Circuits Symposium, 2014 IEEE
Conference_Location :
Tampa, FL
ISSN :
1529-2517
Print_ISBN :
978-1-4799-3862-9
Type :
conf
DOI :
10.1109/RFIC.2014.6851689
Filename :
6851689
Link To Document :
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