32-bit constant (k) coefficient multiplier

Author

Al-Khalili, A.J. ; Zaman, Najam-uz

Author_Institution

Concordia Univ., Montreal, Que., Canada

Volume

1

fYear

2001

fDate

2001

Firstpage

306

Abstract

A 32-bit constant coefficient multiplier using a KCM algorithm in Wallace tree format is presented. The proposed design is compared with other constant coefficient multipliers and different general-purpose multipliers. For quantitative analysis, the multipliers are synthesized in FPGA using Xilinx 4052xl-1 FPGA technology. The analysis presents a guideline to the ASIC designers for selection of an appropriate multiplier when delay, area, power or any combination of them is the primary objective

Keywords

application specific integrated circuits; design engineering; digital signal processing chips; distributed arithmetic; field programmable gate arrays; integrated circuit design; trees (mathematics); ASIC; DSP architecture; ROM; Wallace tree format; Xilinx 4052xl-1 FPGA; area; carry save adders; constant coefficient multiplier; delay; distributed arithmetic architecture; general-purpose multipliers; power; quantitative analysis; Application specific integrated circuits; Arithmetic; Delay; Digital signal processing chips; Discrete Fourier transforms; Discrete cosine transforms; Energy consumption; Field programmable gate arrays; Guidelines; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2001. Proceedings of IEEE Region 10 International Conference on Electrical and Electronic Technology

Print_ISBN

0-7803-7101-1

Type

conf

DOI

10.1109/TENCON.2001.949602

Filename

949602