A 2.5 Gbit/s pipelined routing engine for input-queued ATM switches

Author

Jeong, Gab ; Lee, Jung-Hee ; Lee, Bhum

Author_Institution

Sch. of Comput. & Electron. Eng., Kyongju Univ., South Korea

Volume

1

fYear

2001

fDate

2001

Firstpage

377

Abstract

This paper presents the design of a 2.5 Gbit/s pipelined virtual output queue routing engine for an input-queued ATM switch, which has a serial crossbar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array chip with a 77 MHz operating frequency, a 900-pin fine ball grid array package, and 16×16 switch size

Keywords

asynchronous transfer mode; ball grid arrays; buffer storage; data communication; field programmable gate arrays; queueing theory; telecommunication congestion control; telecommunication network routing; 2.5 Gbit/s; 77 MHz; central arbiter; data transmission latency; field programmable gate array chip; fine ball grid array package; high-speed shifter; input-queued ATM switch; pipelined buffer management; pipelined routing engine; request control method; serial crossbar structure; virtual output queue routing; wire-speed routing; Asynchronous transfer mode; Centralized control; Data communication; Delay; Electronics packaging; Engines; Field programmable gate arrays; Frequency; Routing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2001. Proceedings of IEEE Region 10 International Conference on Electrical and Electronic Technology

Print_ISBN

0-7803-7101-1

Type

conf

DOI

10.1109/TENCON.2001.949617

Filename

949617