A 0.5–6 GHz 25.6 dBm fully integrated digital power amplifier in 65-nm CMOS

Author

Hongrui Wang ; Hashemi, Hossein

Author_Institution

Dept. of Electron. Eng., Univ. of Southern California, Los Angeles, CA, USA

fYear

2014

fDate

1-3 June 2014

Firstpage

409

Lastpage

412

Abstract

This paper presents a 0.5-6 GHz fully-integrated Digital Power Amplifier (DPA) in 65 nm CMOS technology. Transformer-based class-E/F power amplifiers with zero-voltage switching are designed to achieve high power and high efficiency across a wide frequency band. A Single-Pole Triple-Throw (SP3T) switch featuring low insertion loss and high isolation is implemented to select the output of one of the three sub-band DPAs covering approximately 0.5-1.3 GHz, 1.3-3.2 GHz, and 3.2-6 GHz, respectively. Measurement results show a peak output power of 25.6-22.8 dBm with a peak drain efficiency of 34%-20% across 0.5-6 GHz.

Keywords

CMOS analogue integrated circuits; MMIC power amplifiers; UHF integrated circuits; UHF power amplifiers; switches; switching circuits; transformers; CMOS technology; DPA; SP3T switch; efficiency 34 percent to 20 percent; frequency 0.5 GHz to 6 GHz; fully integrated digital power amplifier; peak drain efficiency; single-pole triple-throw switch; size 65 nm; transformer-based class-E-F power amplifier; zero-voltage switching; CMOS integrated circuits; Impedance; Power generation; Power measurement; Switches; Switching circuits; Wideband; CMOS; Digital power amplifier; load modulation; software defined radio; transformer combiner;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium, 2014 IEEE

Conference_Location

Tampa, FL

ISSN

1529-2517

Print_ISBN

978-1-4799-3862-9

Type

conf

DOI

10.1109/RFIC.2014.6851754

Filename

6851754