Optimized scheduling and mapping of logarithm and arctangent functions on TI TMS320C67X processor

DSP processors have gained more importance and popularity in implementing communication systems. Efficient implementation of logarithm and arctangent functions on DSP processors is necessary for applications such as digital receiver used in modern radar systems and digital communication systems. This paper presents a general scheduling and mapping optimization method based on grain packing to implement the two functions on TI TMS320C67X architecture with multiple parallel function units. Experimental results of our optimized implementation on TMS320C67x have achieved up to 79.5% performance improvement over TI C67x library functions. Our optimization method and techniques can also be applied to other DSP processors with parallel execution units.