Productivity improvement through systematic process window identification

For development and production of advanced nodes, systematic pattern failure must be well understood to enable quick device introduction. For 45 nm, use of OPC created tremendous challenges in both optimization and validation of proper amount of optical correction needed. For 32 nm and beyond, immersion and Double Patterning Lithography (DPL) have brought new challenges in controlling process for reaching the entitlement yield. Today lithography engineers are utilizing various approaches to understand the process window that includes CD metrology and defect inspection using special wafers where Focus and Exposure conditions are modulated, however analysis of such wafer requires extensive time and efforts. A systematic and automated approach is required.