Immersion lithography process improvements by wafer edge inspection at 300mm DRAM manufacturing fab

Edge die yield is becoming critical as semiconductor manufacturing fabs attempt to save costs and reduce wafer edge exclusion to produce more good die per wafer. As a consequence, wafer edge defect inspection and metrology applications are now critical components of the overall yield management strategy in advanced semiconductor fabs. Photolithography is the area most affected by defect formation at the wafer edge because of the continuous evolution in process and materials. In this paper, we investigate wafer edge defectivity and film z-height metrology in order to optimize processes and better understand the mechanisms of wafer edge defectivity in the immersion lithography module.