On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs

Author

Chun-Chuan Chi ; Bing-Yang Lin ; Cheng-Wen Wu ; Min-Jer Wang ; Hung-Chih Lin ; Ching-Neng Peng

Author_Institution

Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

31

Issue

4

fYear

2014

fDate

Aug. 2014

Firstpage

16

Lastpage

26

Abstract

This article discusses a design-for-test (DFT) architecture for detecting and repairing faulty interconnects in 3-D IC circuits utilizing through silicon via (TSV) and interposer technology. The yield of such circuits depends highly on the ability to have functioning interconnects which connect the various dies. The authors also propose a built-in-self-test (BIST) framework to enable at-speed testing of such interconnects.

Keywords

built-in self test; design for testability; fault diagnosis; integrated circuit interconnections; integrated circuit testing; three-dimensional integrated circuits; 3D IC circuit; BIST framework; DFT architecture; TSV technology; built-in-self-test framework; defect diagnosis resolution interconnection; design-for-test architecture; interposer technology; through silicon via technology; Built-in self-test; Integrated circuit interconnections; Maintenance engineering; Redundancy; Three dimensional displays; Through-silicon vias; 3D-IC; TSV; defect diagnosis; interconnect BIST; interconnect repair; interposer test; yield enhancement;

fLanguage

English

Journal_Title

Design & Test, IEEE

Publisher

ieee

ISSN

2168-2356

Type

jour

DOI

10.1109/MDAT.2014.2304437

Filename

6731552