DocumentCode :
1756354
Title :
Low-precision DSP-based floating-point multiply-add fused for field programmable gate arrays
Author :
Amaricai, A. ; Boncalo, O. ; Gavriliu, Constantina-Elena
Author_Institution :
Comput. Eng. Dept., Univ. Politeh. of Timisoara, Timisoara, Romania
Volume :
8
Issue :
4
fYear :
2014
fDate :
41821
Firstpage :
187
Lastpage :
197
Abstract :
Floating-point (FP) multiply-add fused (F1*F2±F3) and multiply-accumulate represent the most common arithmetic operation in a wide range of applications, such as graphic processing, multimedia or FP digital signal processing (DSP). This study proposes FP multiply-add fused units for low-precision formats (IEEE 16-bit half precision or the 32-bit single precision) which rely on modern Field Programmable Gate Array (FPGA) features such as the available integer multiply-accumulate-based support built-in the FPGA DSP blocks. These are employed as building-blocks within the mantissa data-path processing for the multiplication and the add/subtract operations. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on the addend, and, a right shift for one of the multiplicands. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are obtained for the multiply-add fused operation.
Keywords :
field programmable gate arrays; floating point arithmetic; multiplying circuits; DSP blocks; FP multiply-add fused units; field programmable gate arrays; low-precision DSP-based floating-point multiply-add fused; low-precision formats; mantissa data-path processing; multiply-add fused operation; multiply-add stage;
fLanguage :
English
Journal_Title :
Computers & Digital Techniques, IET
Publisher :
iet
ISSN :
1751-8601
Type :
jour
DOI :
10.1049/iet-cdt.2013.0128
Filename :
6853135
Link To Document :
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