Title :
Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications
Author :
Xing Hu ; Guihai Yan ; Yu Hu ; Xiaowei Li
Author_Institution :
State Key Lab. of Comput. Archit., Inst. of Comput. Technol., Beijing, China
Abstract :
Voltage emergency (VE) has become a critical challenge with decreasing feature size and increasing power capacity. Destructive core interference is one main source of VE in multicore processors. We observed that the applications following single program and multiple data programming model tend to spark domain-wide destructive core interference because multiple threads exhibit similar power activity. We analyze and quantify this effect and propose one low-cost solution, Orchestrator, to avoid voltage droop synergy among cores. Orchestrator leverages the thread diversity to smooth voltage droops in multicore architectures based on thread scheduling. The thread migration impact on performance is also considered. Experimental results show that Orchestrator can significantly reduce VEs, thereby improving performance.
Keywords :
multi-threading; multiprocessing programs; multiprocessing systems; power aware computing; Orchestrator; decrease feature size; domain-wide destructive core interference; increase power capacity; multicore architectures; multicore processors; multithreaded applications; power activity; single program-and-multiple data programming model; voltage droops; voltage emergencies; Instruction sets; Interference; Message systems; Multicore processing; Pipelines; Synchronization; Multicore; multithreaded application; single program multiple data (SPMD); voltage emergencies (VEs); voltage emergencies (VEs).;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2013.2296787