DocumentCode :
1759583
Title :
Write-Optimized STT-MRAM Bit-Cells Using Asymmetrically Doped Transistors
Author :
Choday, Sri Harsha ; Gupta, Suneet K. ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
35
Issue :
11
fYear :
2014
fDate :
Nov. 2014
Firstpage :
1100
Lastpage :
1102
Abstract :
Spin-transfer torque MRAM (STT-MRAM) is a potential candidate for replacing SRAMs in last level on-chip caches. However, it comes with high write power and oxide reliability issues due to large current required to achieve high speed switching. In this letter, we propose a technique to mitigate the conflict between write-ability and write power of STT MRAM using an access transistor with asymmetric doping at the source/drain terminals. Our technique achieves 35% write power reduction at iso-write speed. In addition, the maximum voltage drop across the tunnel barrier in the Magnetic Tunnel Junction reduces by 23% which improves its reliability.
Keywords :
MRAM devices; circuit optimisation; low-power electronics; magnetic tunnelling; semiconductor doping; transistor circuits; SRAM; access transistor; doped transistors; high speed switching; isowrite speed; magnetic tunnel junction; on-chip caches; oxide reliability; power reduction; source-drain terminals; spin-transfer torque MRAM; tunnel barrier; write power; write-ability; write-optimized STT-MRAM bit-cells; Doping; FinFETs; Magnetic tunneling; Reliability; Resistance; Switches; STT-MRAM; asymmetric FinFET; write power;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2014.2358998
Filename :
6915720
Link To Document :
بازگشت