Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating

A technique is presented to prevent timing errors under transient noise by borrowing time over multiple stages and by compensating once by delaying the clock gating over multiple cycles from the time-borrowing detection point. A logic network is presented for programming the number of stages n, over which time borrowing is performed to trade off supply noise tolerance with a performance penalty. The constraint that is associated with the control delay from the time-borrowing detection to the clockgating circuit is also relaxed to n cycles. The technique is referred to as the programmable time borrowing (PTB) technique, as time borrowing is performed over a programmable number of stages. A test chip with a five-stage pipeline employing the PTB is designed in the 130-nm CMOS technology, and the measurement results demonstrate improved noise tolerance and effective performance.