Low complexity twiddle factor multiplication with ROM partitioning in FFT processor

Proposed is a low-complexity twiddle factor multiplication structure for fast Fourier transform (FFT). In an FFT implementation, the twiddle factor multiplication requires a large ROM to store the twiddle factors. In the proposed structure, the ROM is partitioned into two small ROMs, whose sum of areas is much smaller than that of the original ROM. The proposed structure requires an additional multiplier, but the multiplier is shown to be small in the experimental results. The results show that the proposed structure reduces the area of the twiddle factor multiplication by around 30% with a marginal degradation in SQNR performance.