Design and Analysis of a High-Efficiency High-Voltage Class-D Power Output Stage

Author

Haifeng Ma ; van der Zee, R. ; Nauta, Bram

Author_Institution

CTIT Inst., Univ. of Twente, Enschede, Netherlands

Volume

49

Issue

7

fYear

2014

fDate

41821

Firstpage

1514

Lastpage

1524

Abstract

The analysis and design of a highly-efficient 80 V class-D power stage design in a 0.14 μm SOI-based BCD process is described. It features immunity to the on-chip supply bounce, realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and low switching loss are achieved with 94% peak efficiency for the complete class-D power stage in the realized chip.

Keywords

BIMOS integrated circuits; driver circuits; power amplifiers; silicon-on-insulator; SOI based BCD process; class D power stage design; gate driver; high voltage class-D power output stage; on chip supply bounce; regulated floating supply; size 0.14 mum; variable driving strength; voltage 80 V; Logic gates; Power transistors; Soft switching; Switches; Switching circuits; System-on-chip; Transistors; BCDMOS; CMOS; class-D amplifier; gate driver; hard switching; high efficiency; high-voltage; level shifter; on-chip regulator; output stage; soft switching; supply bouncing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2317780

Filename

6808419