Exploration of Lattice Reduction Aided Soft-Output MIMO Detection on a DLP/ILP Baseband Processor

Lattice Reduction aided soft output MIMO detectors (LR-SOMD) have been demonstrated to offer a promising gain. This work explores the potential of implementing a LR-SOMD on a parallel programmable baseband processor. In this paper, first a LR algorithm called the Data Regularized Parallel Lattice Reduction algorithm (DRP-LR) is proposed. Afterwards, a low-complexity LR-SOMD, Radius Constrained Multi-Tree Selective Spanning (RC-MTSS) is presented. RC-MTSS uses a novel multiple-tree search approach for LR-SOMD, while combining the benefits of Sphere Detection (SD) and Selective Spanning with Fast Enumeration (SSFE). A fixed complexity LR-SOMD, Multi-Tree Selective Spanning (MTSS) is also proposed for implementation. Both the algorithms, DRP-LR and MTSS, are enabled to exploit data level parallelism (DLP) and instruction level parallelism (ILP). In order to evaluate performance, the proposed DRP-LR and MTSS are implemented on the ADRES baseband processor for a 4 × 4 LTE system using QAM-64. DRP-LR achieves an average throughput of 33.33 M LR per second, which is comparable to recently reported ASIC implementations, while MTSS shows an average throughput of 730 Mbps on the same processor. To the best of authors´ knowledge, this is the first reported implementation of a LR-SOMD algorithm on a parallel programmable baseband processor.