An optimised processor for FMCW radar

This paper presents a digital signal processor architecture optimized for FMCW radar systems, as used in automotive, security and surveillance applications. The novel architecture is described, along with the size, power consumption and performance for key radar processing operations. Architecture features include a flexible compute unit optimized for FFT operations and a two-dimensional register file. An FPGA implementation of the processor is used to demonstrate range-Doppler processing in real-time.