Title :
Design of multi-stage latency adders using detection and sequence-dependence between successive calculations
Author :
Xinghua Yang ; Fei Qiao ; Chang Liu ; Qi Wei ; Huazhong Yang
Author_Institution :
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Abstract :
Multi-stage latency adders based on different prediction schemes have been proved promising to enhance the circuit performance with negligible overhead. This paper presents a novel predictor exploiting both the detection and the sequence-dependence between the successive calculations. The detection of carry-kill pattern of the input data can lower the probability of the operation with multiple clock cycles and the sequence-dependence between the successive calculations is adapted to eliminate redundant cycles. The improved predictors have been inserted into Ripple Carry Adder (RCA) and a multistage latency structure has been setup. Compared with the previous predictors, the proposed one could have the same function with less prediction bits, which results in more energy-efficiency. Simulation results show that 2.41X-3.05X speedups can be achieved than the non-prediction counterpart. Furthermore, a design flow and a method for error control are proposed when applying the adder to approximate computation so that more performance improvement could be obtained after trading off certain precision.
Keywords :
adders; logic design; prediction theory; RCA; carry-kill pattern; design flow; error control; multiple clock cycles; multistage latency adders; multistage latency structure; prediction schemes; redundant cycles elimination; ripple carry adder; sequence-dependence; successive calculations; Adders; Clocks; Delays; Equations; Error correction; Logic gates; Prediction methods;
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865306