DocumentCode :
1768924
Title :
Optimized cubic chebyshev interpolator for elementary function hardware implementations
Author :
Sadeghian, Masoud ; Stine, James E. ; Walters, E. George
Author_Institution :
Dept. of Electr. & Comput. Eng., Oklahoma State Univ., Stillwater, OK, USA
fYear :
2014
fDate :
1-5 June 2014
Firstpage :
1536
Lastpage :
1539
Abstract :
This paper presents a cubic interpolator for computing elementary functions using truncated-matrix arithmetic units and an optimized number of coefficients bits. The proposed method optimizes the initial coefficient values found using a Chebyshev series approximation, minimizing the maximum absolute error of the interpolator output. The resulting designs can be utilized for approximating any function up to 53-bits of precision (IEEE double precision significant). Area, delay and power estimates are given for 16, 24 and 32-bit cubic interpolators that compute the reciprocal function, targeting a 65nm CMOS technology from IBM. Results indicate the proposed method uses smaller arithmetic units and has reduced lookup table sizes than previously proposed methods.
Keywords :
CMOS integrated circuits; Chebyshev approximation; digital arithmetic; interpolation; matrix algebra; series (mathematics); CMOS technology; Chebyshev series approximation; coefficient bit optimized number; elementary function hardware functions; interpolator output; maximum absolute error minimization; optimized cubic Chebyshev interpolator; reduced lookup table sizes; size 65 nm; truncated-matrix arithmetic units; word length 16 bit; word length 24 bit; word length 32 bit; Chebyshev approximation; Delays; Function approximation; Hardware; Optimization methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
Type :
conf
DOI :
10.1109/ISCAS.2014.6865440
Filename :
6865440
Link To Document :
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